It has come to my attention that the User's Guide for 1.8 does not document the IP-Import feature.
I have attempted to document the steps here (with the help of our engineering staff, of course). There aren't many steps, so it is pretty easy.
1. Select File->Open Template->Slave. Along with importing signals, this creates a slave bus interface, an empty memory map for registers, and links the slave interface to the memory map. Alternatively one may choose master creates a master bus interface, and empty address space, and links the master interface to the address space.
2. The user is prompted to select the top-level VHDL or Verilog file with a standard file select dialog.
3. The user is then prompted to select the rest of the files with a standard multiple-pick file select dialog (i.e, shift-click and ctrl-click and other multi-choose options work with this dialog).
Apart from the things created in step 1, this creates a signal for each signal in the top-level file, a fileset containing all of the files from steps 2 and 3 (if the file in 2 is selected again in 3, it is not added a second time), a reasonable guess at the type of each file, and a view linked to the fileset.
In the upcoming 2.0 release we are planning to eliminate step 2 - we should be able to figure out which file from step 3 is a top-level file. Also we are improving step 3 such that it will repeat until the user clicks cancel.
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